1. Field of the Invention
The present invention relates to the field of display, and in particular to a gate driver on array (GOA) circuit.
2. The Related Arts
As the liquid crystal display (LCD) shows the advantages of being thin, low power-consumption, and no radiation, the LCD is widely used in various devices, such as, liquid crystal TV, mobile phones, PDA, digital camera, PC monitors or notebook PC screens as well as the leading technology in tablet PCs.
The gate driver on array (GOA) technology is the array substrate column drive technology, by using the array substrate process for the LCD panel to manufacture the driver circuit for the horizontal scan line in the area around the active area on the substrate to replace the external integrated circuit (IC) to perform driving the horizontal scan lines. GOA technology can reduce the bonding process for the external IC and reduce cost, as well as the ability to realize narrow-border or borderless panels, and is used by many types of displays.
Refer to FIG. 1. A known GOA circuit comprises: a plurality of cascade GOA units, with each GOA unit comprising: a forward-and-reverse scan control module 100, an output module 200 and a node control module 300; for a positive integer n, in the n-th stage GOA unit, the forward-and reverse scan control module 100 comprising: a first thin film transistor (TFT) T1, with the gate connected to the gate scan drive signal G(n−2) of the (n−2)-th stage GOA unit, the source connected to forward scan control signal U2D, and the drain connected to a first node H(n); and a third TFT, with the gate connected to the gate scan drive signal G(n+2) of the (n+2)-th stage GOA unit, the source connected to reverse scan control signal D2U, and the drain connected to a first node H(n); The output module 200 comprising: a second TFT T2, with the gate connected to the second node Q(n), the source connected to the m-th clock signal CK(m), and the drain connected to the gate scan drive signal G(n) of the n-th stage GOA unit, and a first capacitor C1, with one end connected to the second node Q(n), and the other end connected to the gate scan drive signal G(n) of the n-th stage GOA unit; the node control module 300 comprising: a fourth TFT T4, with the gate connected to a third node P(n), the source connected to the gate scan drive signal G(n) of the n-th stage GOA unit, and the drain connected to a constant low voltage VGL; a fifth TFT T5, with the gate connected to a constant high voltage VGH, the source connected to the first node H(n), and the drain connected to the second node Q(n); a sixth TFT T6, with the gate connected to the third node P(n), the source connected to the first node H(n), and the drain connected to the constant low voltage VGL; a seventh TFT T7, with the gate connected to the first node H(n), the source connected to the third node P(n), and the drain connected to the constant low voltage VGL; an eighth TFT T8, with the gate connected to the (m+2)-th clock signal CK(m+2), the source connected to the constant high voltage VGH, and the drain connected to the third node P(n); and a second capacitor C2, with one end connected to the third node P(n) and the other end connected to the constant low voltage VGL.
In the known GOA circuit in FIG. 1, the first TFT T1 and the third TFT T3 form the forward-and-reverse scan control module 100. The first TFT T1 and the third TFT T3 must be connected respectively to the forward scan control signal U2D and reverse scan controls signal D2U. During forward scanning, the forward scan control signal U2D is high and the reverse scan control signal D2U is low; during reverse scanning, the forward scan control signal U2D is low and the reverse scan control signal D2U is high. As such, the integrated circuit (IC) must provide the capability of outputting the control signals, which limits the selection range of the IC. Also, because of the existence of the forward scan control signal U2D and reverse scan controls signal D2U, the layout is difficult to realize narrow-border LCD.